In modern high-speed logic circuits, the requirements for meeting default timings at the inputs and outputs are very strict. Hence, the corresponding input and output drivers are very important today. In order to illustrate the problems occurring in the operation of an output driver, an exemplary output circuit according to the prior art will be described in greater detail in the following.
FIG. 6 shows a simplified circuit diagram of an output driver of a microelectronic circuit according to the prior art in connection with an excitation source. The overall circuit arrangement is designated with 610. It includes an excitation source 620 as well as a driver circuit 622. The excitation source 620 includes a first inverter 630 the data input D of which is controlled by a pseudo random data signal (PRBS) source 632. The pseudo random data generator 632 provides pseudo random data at a bit rate of 1.6 Gbps. The first inverter 630 is coupled to a first supply potential VDD and a first reference potential VSS, wherein the potential difference between the first supply potential VDD and the first reference potential VSS is 1.8 volt in the example shown. This voltage supply is impressed from outside and is symbolically shown by a direct voltage source 634. Furthermore, it is to be noted that the first reference potential VSS is connected to a global reference potential GND. Furthermore, it is to be noted that the n-channel MOS field effect transistor of the first inverter 630 has a channel width of 2 μm, whereas the p-channel MOS field effect transistor of the first inverter 630 has a channel width of 4.5 μm. The inverters of the shown circuit are conventional CMOS inverters, as shown in the legend 640. In order to achieve equal rise and fall times, the accompanying p-channel MOS field effect transistors and n-channel MOS field effect transistors have different channel widths, which are correspondingly labeled in FIG. 6.
The driver circuit 622 includes two series-connected inverters 650, 652 coupled to a second supply potential VDDQ and a second reference potential VSSQ. The input of the second inverter 650 is coupled to the output of the first inverter 630 of the excitation source 620. The output of the second inverter provides a control signal DX for the third inverter 652. The output of the third inverter 652 is coupled to the circuit output 656. The potential difference between the second supply potential VDDQ and the second reference potential VSSQ is a constant 1.8 volts, which is characterized by the direct voltage source 660. The second reference potential VSSQ is not identical with the global reference potential GND, but is coupled thereto via a noise voltage source 670 in the given modeling. In the given modeling, the noise voltage source provides a sinusoidal voltage signal with an amplitude of 0.35 volts and a frequency of 1 gigahertz. In the given circuit, the output voltage 680 is defined or tapped between the second reference potential VSSQ and the circuit output 656.
Based on the structural description, the functioning of a conventional output driver circuit 610 will be described in the following. It is the object of the circuit shown to make an internal signal, present at the data input D, available at an external bus attached at the circuit output 656 in well-defined manner in buffered form. The signal at the data input D has transitions between the potentials VDD (logically HIGH) and VSS (logically LOW). The output buffer formed by the driver circuit 622 is supplied via separate potential supplies (power rails) providing the second supply potential VDDQ as well as the second reference potential VSSQ. The separation between internal supply potentials including the first supply potential VDD as well as the first reference potential VSS and external supply potentials including the second supply potential VDDQ as well as the second reference potential VSSQ is necessary because the external supply potentials, i.e. VDDQ and VSSQ, are subject to irregular fluctuations caused by inductances, when the buffer drives the external bus. In a typical operation of a device or an integrated circuit, it is helpful to decouple these statistical fluctuations from the on-chip potential rails guiding the first supply potential VDD and the first reference potential VSS. In the following, it is assumed that in a static case the first supply potential VDD is equal to the second supply potential VDDQ, and that the first reference potential VSS is equal to the second reference potential VSSQ (VDDQ=VDD; VSSQ=VSS).
In order to be able to meet strict specifications with reference to the output-side timings, it is important to ensure that the propagation time delay by the buffer is constant at all events. For example, if a rising edge propagates more quickly through the buffer than a falling edge, the output-side timings between the rising and falling edges would be temporally shifted relative to each other.
Furthermore, fluctuating or noisy voltages significantly contribute to shifts in the timings. Although a capacitive coupling between the first supply potential VDD and the first reference potential VSS as well as between the second supply potential VDDQ and the second reference potential VSSQ, which exists on a chip, may ensure that the potential differences between the first supply potential VDD and the first reference potential VSS as well as between the second supply potential VDDQ and the second reference potential VSSQ are constant, but the relations between the first supply potential VDD and the second reference potential VSSQ (VDD-VSSQ) as well as between the second supply potential VDDQ and the first reference potential VSS (VDDQ-VSS) are not well-controlled at the presence of statistical disturbances on the second supply potential VDDQ and the second reference potential VSSQ induced by inductances. Hence, each transistor working at the boundary between circuit domains supplied with the first supply potential VDD and the first reference potential VSS and circuit domains supplied with the second supply potential VDDQ and the second reference potential VSSQ contributes a signal propagation time sensitive to statistical fluctuations of the supply and reference potentials.
The example according to the prior art shown on the basis of FIG. 6 is a starting basis for a simulation with the Agilent Technologies simulation software ADS. In this simulation, statistical fluctuations (noise) caused by inductances on the second supply potential VDDQ and the second reference potential VSSQ are modeled by a voltage source providing a sinusoidal voltage with an amplitude of 0.35 volts and a frequency of one gigahertz. The pseudo random data generator 632 providing a data stream at a bit rate of 1.6 gigabits per second (1.6 Gbps) here serves as excitation for the simulated circuit arrangement 610. Here, the output voltage 680 between the circuit output 656 and the second reference potential VSSQ is observed.
FIG. 7 shows an extract from a simulated eye diagram for an output driver according to the prior art. The eye diagram in its entirety is designated with 710. Here, the data eye for the output voltage 680 is shown at a transition from a low logic level to a high logic level and vice versa. The abscissa 720 shows the time in ps, wherein a period of time from 0 to 625 ps is shown here. The ordinate 722 shows the output voltage 680 and is scaled in volts.
In the previously described circuit modeling, the eye diagram 710 shows a jitter 730 of 75 ps on the output voltage 680. This jitter 730 is caused by the transition from a circuit domain supplied with the first supply potential VDD to a circuit domain supplied with the second supply potential VDDQ (VDD-VDDQ domain transition).
For better understanding it is here also gone into some details of the circuit function. On the one hand, it is important to view the differences between the two voltage supplies. An integrated circuit arrangement modulated by the excitation source 620 in the circuit arrangement 610 shown on the basis of FIG. 6 is operated at a power supply that is only subject to small fluctuations (low noise power supply). The potential difference between the accompanying first supply potential VDD and the first reference potential VSS is approximately constant. In practice, this is ensured by capacities existing on a chip between the corresponding supply lines or supply layers. The first supply potential VDD and the first reference potential VSS are largely fixed also with reference to a global reference potential GND and only subject to small fluctuations. On the other hand, the second supply potential VDDQ as well as the second reference potential VSSQ represent a fluctuating power supply (noisy power supply). The potential difference between the second supply potential VDDQ and the second reference potential VSSQ is here again approximately constant by capacities, but the two potentials fluctuate with reference to a global reference potential GND.
Furthermore, in the following, it is gone into how a switching operation at the transition between the circuit domain supplied with the first supply potential VDD and the circuit domain supplied with the second supply potential VDDQ takes place. What is viewed here is the handover of a signal from the first inverter 630 to the second inverter 650. The first inverter 650 here includes a pMOS field effect transistor, the source terminal of which is connected to the second supply potential VDDQ, as well as an nMOS field effect transistor, the source terminal of which is connected to the second reference potential VSSQ. Here, a discharge operation, in which a capacity at the input of the third inverter 652 is discharged, and a charge operation, in which a capacity at the input of the third inverter 652 is charged, is considered. Charge operation and discharge operation represent the two state transitions possible and determine the steepness and temporal location of the switching edges.
A discharge operation is initiated by the output of the first inverter supplied by the first supply potential VDD taking on a logically HIGH level. The output of the first inverter thus is at or close to the first supply potential VDD. This potential is also present at the gate terminals of the MOS field effect transistors of the second inverter 650. Here, the nMOS field effect transistor of the second inverter 650, the source terminal of which is at the second reference potential VSSQ, is relevant for the discharge operation. The potential difference between the first supply potential VDD and the second reference potential VSSQ is decisive for the current flow through the nMOS field effect transistor, which discharges a capacity of the third inverter 652.
Similarly, a charge operation is initiated by the output of the first inverter 630 assuming a logically LOW state. This means that the output of the first inverter 630 is at the first reference potential VSS or very close thereto. The pMOS field effect transistor of the second inverter 650 is responsible for the charge operation of a capacity at the input of the third inverter 652. The first reference potential VSS is present at its gate, whereas the second supply potential VDDQ is present at a source terminal. The potential difference between the second supply potential VDDQ and the first reference potential VSS here is responsible for the charge current.
Shifts between the first supply potential VDD and the second supply potential VDDQ or between the accompanying first reference potential VSS and the accompanying second reference potential VSSQ lead to the fact that the charge and discharge currents, respectively, are changed with reference to a desired nominal state. Depending on the potential difference between the first and second potentials, thus a temporal shift of edges develops at a switching transition. It is especially disturbing here that the edges shift differently for rising and falling switching transitions. Thereby predetermined timings are disturbed.
According to the prior art, a series of solutions are known, which are supposed to guarantee constant signal propagation time at a transition between circuit domains with different supply voltages. Since the basic reason for the propagation time changes induced by statistical potential fluctuations is the statistical potential variations on a chip induced by inductances, simple solutions aim at directly minimizing the statistical potential fluctuations (noise). This may be achieved in simple manner by a decrease in the overall inductance on the potential supplies for the second supply potential VDDQ and the second reference potential VSSQ (VDDQ/VSSQ power rails). A decrease in the overall inductance is possible either by an increase of the number of connections for the second supply potential VDDQ and the second reference potential VSSQ or by the use of a better package. In the first solution, several inductances are connected in parallel, whereby the overall inductance decreases, in the latter solution the inductance per connection is lower. Both solutions, however, are of limited practical use, since they result in a more expensive product.
A further solution for the improvement of the time domain properties is described in the conference contribution “Digitally-Controlled DLL and I/O Circuits for 500 Mb/s/pin×16 DDR SDRAM”, ISSCC 2001, pages 68 f., by J. B. Lee et al. In this article it is proposed to displace the boundary between the circuit domains supplied with a first supply potential and the circuit domains supplied with a second supply potential (domain transition) from the input of the last driver stage to the input of the pre-driver. This solution reduces the magnitude of the introduced propagation time differences but is not capable of eliminating them completely, because voltage differences subject to statistical fluctuations continue existing at the input of the pre-driver. The improvements achievable by such a circuit arrangement are already to be seen in FIG. 7, because the transition between circuit domains with different supply potentials (domain transition) is not situated at the input of the last driver stage but already at the input of the pre-driver in the simulated circuit arrangement 610 according to FIG. 6.
A further solution for the decrease of temporal insecurities may for example be derived from the conference contribution “Level Converters with High Immunity to Power-Supply Bouncing for High-Speed sub-1-V LSIs”, Symposium VLSI Circuits 2000, pages 202 f., by Y. Kanno et al. This article teaches the use of a level converter to provide a transition from a circuit domain supplied with a first supply potential to a second circuit domain supplied by a second supply potential. Level converters have to be used if the first supply potential VDD is more negative than the second supply potential VDDQ (VDD<VDDQ). If in a static operating state, however, the first supply potential VDD is equal to the second supply potential VDDQ (VDD=VDDQ), and the first reference potential VSS is also equal to the second reference potential VSSQ (VSS=VSSQ), the realization of a level converter is typically avoided, because level converters introduce an additional time delay in the output path and are only difficult to design without propagation time differences.